The IPSiLog Semiconductor GmbH serial SRAM family IP12xxxxx includes several integrated memory devices including this 512Kb serially accessed (SPI-Compatible Interface (Mode0 and Mode3)) Static Random Access Memory, internally organized as 64K words by 8 bits each.
The IP12B512C-T and IP12B512I-T products have the following features:
- Max Clock 20MHz
- SPI-Compatible Interface (Mode0 and Mode3)
- Operating current: max. 2mA @ 1MHz
- Standby current: typ. 10uA @ +25°C
- 65.536 x 8-bit Organisation
- 32-Byte Page
- Hold pin for pausing communication
- Sequential Read/Write
- Flexible operating modes: Byte read and write (BYTE), Page mode (PAGE), Pagestart Sequential mode (PSEQ), Virtual chip mode (VRTM)
- Infinite read/writes to memory array